1. Technical Field
The present invention relates in general to the field of data processing systems. More specifically, the present invention relates to managing bus transactions on data processing systems. Still more specifically, the present invention relates to a system and method of implementing multiple internal virtual channels based on a single external virtual channel in a data processing system.
2. Description of the Related Art
Introduced in the early 1990s, the Peripheral Component Interconnect (PCI) bus unified the diverse input/output (I/O) buses available on personal computers (PCs) at the time. Some of these I/O buses included the Video Electronics Standards Association (VESA) local bus, Extended Industry Standard Architecture (EISA), Industry Standard Architecture (ISA), and Micro Channel Architecture (MCA). Initially, the PCI bus was implemented as a chip-to-chip interconnect and a replacement for the fragmented ISA bus. During the first years of implementation, the 33 MHz PCI bus adequately served the I/O bandwidth requirements of mainstream peripherals. Today, however, processor and memory clock frequencies have increased dramatically, with processor clock speeds increasing at a more aggressive rate.
In the early 2000s, the PCI Express (PCIe) architecture was introduced. PCIe is an implementation of the PCI bus that utilizes existing PCI programming concepts, but utilizes a different and faster serial physical-layer communications protocol. However, when a PCIe bridge is coupled to a collection of devices, slower devices may prevent high-performance devices from obtaining the bandwidth that they require. Therefore, there is a need for a system and method of addressing the abovementioned limitations.